A DC-to-DC converter is a circuit or device which converts DC power from one voltage to another voltage. A DC-to-DC converter accepts a DC input voltage and produces a DC output voltage. Typically the DC output voltage produced is at a different voltage level than the DC input voltage. For instance, a DC-to-DC converter may convert a relatively high input battery voltage to a lower DC output voltage, or vice versa, and in some cases converts the input battery voltage to a negative DC output voltage.
DC-to-DC converters are important in many portable battery-operated electronic devices, such as cellular phones and laptop computers, which are supplied with power from batteries. Such electronic devices often contain several sub-circuits with each sub-circuit requiring a unique DC voltage level from that supplied by the battery. Most battery-operated devices include many different DC-to-DC converters with each DC-to-DC converter generating a controlled DC voltage from a single variable battery voltage. By implementing multiple DC-to-DC converters to generate and control appropriate DC voltages at different points in the circuit space can be saved instead of using multiple batteries to supply different parts of the device.
FIG. 1A is a circuit schematic which illustrates a conventional DC-to-DC converter 100. The DC-to-DC converter 100 consists of a pulse width modulated (PWM) clock 110, an output power switch stage 165, an external LC filter 170 and a feedback loop which includes an error amplifier 198 coupled between an output of the LC filter 10 and the clock 110.
The clock 110 generates a clock signal at a certain frequency and provides it to the power switch stage 165. The power switch stage 165 includes a first (or high-side) PMOS transistor 140 and a second NMOS (or low-side) transistor 150. The transistors 140, 150 each have a parasitic “body” diode 142, 152 in parallel, respectively. The first transistor 140 is couple between an input voltage (Vin) source 133 and a first node 145, whereas the second transistor 150 is coupled between the first nod 145 and ground. Both transistors 140, 150 receive the clock signal as the input at their gate electrode. The clock signal causes the transistors 140, 150 to alternately turn on or turn off, and only one is on at a give time. The transistors 140, 150 to alternately turn on and off with some uncertain or variable delay between receiving the command to turn on/off an the actual turn on/off. When the transistor 140 turns on and the transistor 150 turns off, the transistor 140 generates a high output voltage at the first node 145 which is approximately equal to the input voltage (Vin). When the transistor 140 turns off and the transistor 150 turns on, the transistor 150 generates a low output voltage at the firs ode 145 which is approximately equal to zero volts. In some implementations, the transistors 140, 150 switch on and off at a frequency of approximately on megahertz (MHz). The turn-on and turn-off characteristics of the transistors 140, 150 depend on a variety of factors which can vary with time such as the supply voltages, the temperature, and other variables.
The respective outputs of the first transistor 140 and the second transistor 150 are combined at the first node 145 to generate a square wave voltage (V1). The LC filter 170 include an inductor 160 which is coupled between the first nod 145 and a second node 161, and a capacitor 162 coupled between the second node 161 and ground. The LC filter 170 filters the square wave voltage (V1) to provide a DC output voltage (Vout) at the second node 161. For example, in a scenario where the DC-to-DC converter 100 is required to provide a 2.5 volt voltage at Vout, a duty cycle of the transistors 140, 150 would be 50% so that only the first transistor 140 would be on one-half the time (e.g., providing 5 volts at V1) and only the second transistor 150 would be one-half of the time (e.g., providing 0 volts at V1) Thus, the average output voltage (Vout) at node 161 would be 2.5 volts after passing through the LC filter 170.
To generate and maintain an appropriate DC output voltage (Vout) at a desired level, the feedback loop controls the duty cycle of the clock signal generated by the clock 110 to continuously adjust the duty cycle of the transistors 140 and 150. The error amplifier 198 in the feedback loop receives the actual output voltage (Vout), compares it to a stable reference voltage (Vref) (which is the desired value of the output voltage (Vout)), and generates an error voltage control signal 199 which represents the difference between the actual output voltage (Vout) and the stable reference voltage (Vref). The control signal 199 continuously adjust the actual output voltage (Vout) towards the desired reference voltage (Vref) by changing the duty cycle of the clock 110. This way, the duty cycle of the transistors 140, 150 ensures that the actual output voltage (Vout) is driven to the desired reference voltage (Vref). For instance, when the actual output voltage (Vout) is too high, the control signal 199 reduces the duty cycle of the clock 110 to adjust the duty cycle of the transistors 140, 150 so that the output voltage (Vout) reaches the desired value of the output voltage (Vref).
FIG. 1B is a graph of a waveform which is a simplified representation of the voltage (V1) signal 110 at the first node 145 as a function of time (t). The voltage (V1) signal 110 is substantially periodic and has a period (T). Each interval of the period (T) consists of two subintervals—(t1) and (t2). The time interval (t1) represents the time when the voltage (V1) is either at a low voltage (e.g. below 2.5 volts) or negative voltage (e.g., −0.6 volts), an the time interval (t2) represents the time when the voltage (V1) is at a high level (e.g., above 2.5 volts). The ratio of time interval (t2) to the period (T) is the duty cycle of the voltage (V1). In FIG. 1B, the voltage (V1) is initially at 5 volts. When the transistors 140, 150 receive their respective clock signals, the first transistor 140 switches off and the second transistor 150 begins the process of turning on. Turning the first transistor 140 off causes the voltage (V1) to transition from the high level to the negative level (e.g., −0.6 volts), where the voltage (V1) remains there until the second transistor 150 turns on causing the voltage (v1) to rise to the low level.
If the first transistor 140 and second transistor 150 are simultaneously turned on, even if only for a short interval, a short circuit can occur across the supply. For example, after the second transistor 150 receives the clock signal it may take only five nanoseconds to turn on, but it may take ten nanoseconds to turn off the first transistor 140. Turning the second transistor 150 on before the first transistor 140 is completely turned off can result in the second transistor 150 actually turning on while the first transistor 140 is still turned on. To prevent this scenario, a “deadtime” interval 112 is provided to ensure that a sufficient amount of time elapses between the clock signal to turn of the first transistor 140 and the clock signal to turn on the second transistor 150. (The deadtime interval 112 represents the duration which occurs between the first transistor 140 turning off and the second transistor 150 turning on.) The deadtime interval 112 on the falling edge helps ensure that an adequate time passes after the first transistor 140 has been turned off before the second transistor 150 turns on so that the transistor 140, 150 are not on simultaneously. Absence of the deadtime interval 112 would imply cross conduction of the transistors 140, 150 which is undesirable. In one implementation, the deadtime interval 112 can be approximately 10 to 20 nanoseconds. At the start of the deadtime interval 112, the output voltage (V1) starts off at the high level (e.g., 5 volts) and then decreases to the negative voltage (e.g., −0.6 volts) when the first transistor 140 turns off. After a time period (e.g., ten nanoseconds), the second transistor 150 begins conducting, and the output voltage (V1) returns to the low voltage (e.g., −0.1 volts between the deadlines 112, 114) which is equal to the current flowing through the inductor 360 multiplied by the on-resistance of the second transistor 150.
Thereafter, when the second transistor 150 turns off and the fist transistor 140 has not yet turned on, the output voltage (V1) drops to the negative voltage (e.g., −0.6 volts) and remain at the negative voltage (e.g., −0.6 volts) for the second deadtime interval 114. During the next clock cycle, after a sufficient deadtime interval 144 to ensure that the second transistor 150 has turned off, the first transistor 1540 turns on again, and the output voltage (V1) returns to the high level (e.g., approximately 5.0 volts since the transistor 140 has an on resistance which reduces the voltage (V1)).
Many electronic devices operate on battery power. To increase device lifetime on a single battery charge, it is important to increase the operating efficiency of the DC-to-DC converter 100. (e.g., an efficient conversion of input DC voltage to voltage to output DC voltage). Because battery resources are consumed excessively and are wasted during the deadtime intervals 112 and 114, to increase battery and device lifetime it is desirable to reduce the deadtime interval(s) 112, 114 as much as possible.
Accordingly, it is desirable to provide techniques for optimizing battery life in an electronic device by automatically reducing deadtime intervals(s) to an optimized value/ Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawing and the foregoing technical field and background.